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| 1 of 23 general description the DS2482-800 is an i 2 c-to-1-wire ? bridge device that interfaces directly to standard (100khz max) or fast (400khz max) i 2 c masters to perform bidirectional protocol conversion between the i 2 c master and any downstream 1-wire slave devices. relative to any attached 1-wire slave device, the DS2482-800 is a 1-wire master. internal factory- trimmed timers relieve the system host processor from generating time-critical 1-wire waveforms, supporting both standard and overdrive 1-wire communication speeds. to optimize 1-wire waveform generation, the DS2482-800 performs slew-rate control on rising and falling 1-wire edges and has a programmable feature to mask the fast presence pulse edge that some 1-wire slave devices can generate. programmable strong pullup features support 1-wire power delivery to 1-wire devices such as eeproms and sensors. the DS2482-800 combines these features with eight independent 1-wire i/o channels. the i 2 c slave address assignment is controlled by three binary address inputs, resolving potential conflicts with other i 2 c slave devices in the system. applications wireless base stations central office switches pbxs rack-based servers medical clinical diagnostic equipment typical operating circuit features ? i 2 c host interface, supports 100khz and 400khz i 2 c communication speeds ? 1-wire master i/o with selectable active or passive 1-wire pullup ? provides reset/presence, 8-bit, single-bit, and three-bit 1-wire i/o sequences ? 8 channels of independently operated 1-wire i/o ? standard and overdrive 1-wire communication speeds ? slew controlled 1-wire edges ? supports low-impedance 1-wire strong pullup for eeproms, temp sensors, or other 1-wire slaves that have momentary high current modes ? three address inputs for i 2 c address assignment ? wide operating range: 2.9v to 5.5v, -40c to +85c ? 16-pin so package (150 mils) ordering information part temp range pin- package ds2482s-800+ -40 to +85 ? c 16 so ds2482s-800+t&r -40 to +85 ? c 16 so +denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. pin configuration 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 io2 io1 io0 gnd io4 io5 io6 io7 io3 scl sda v cc nc ad2 ad1 ad0 1-wire is a registered trademark of maxim integrated products, inc. 19-4932; rev 4; 1/12 DS2482-800 8-channel 1-wire maste r
DS2482-800: 8-channel 1-wire master 2 of 23 absolute maximum ratings voltage on any pin relative to ground -0.5v, +6v maximum current into any pin ? 20ma operating temperature range -40c to +85c junction temperature +150c storage temperature range -55c to +125c lead temperature (soldering, 10s) +300c soldering temperature (reflow) +260c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating condi tions for extended periods may affect device reliability. electrical characteristics (v cc = 2.9v to 5.5v, t a = -40c to +85c, unless otherwise noted.) parameter symbol conditions min typ max units supply voltage v cc 3.3v 2.9 3.3 3.7 v 5v 4.5 5.0 5.5 operating current i cc (note 1) 0.75 ma 1-wire input high v ih1 3.3v (notes 2, 3) 1.9 v 5v (notes 2, 3) 3.4 1-wire input low v il1 3.3v (notes 2, 3) 0.75 v 5v (notes 2, 3) 1.0 1-wire weak pullup resistor r wpu (note 4) 800 1675 ? 1-wire output low v ol1 at 4ma load 0.4 v active pullup on time t apuot standard (notes 4, 16) 2.3 2.5 2.7 s overdrive (notes 4, 16) 0.4 0.5 0.6 strong pullup voltage drop ? v strpu v cc ? 3.2v, 1.5ma load 0.3 v v cc ? 5.2 v, 3ma load 0.5 3.3v pulldown slew rate (note 6) pd src standard (3.3v ? 10%) 1 4.2 v/s overdrive (3.3v ? 10%) 5 22.1 5v pulldown slew rate (note 6) pd src standard (5.0v ? 10%) 2 6.5 v/s overdrive (5.0v ? 10%) 10 40 3.3v pullup slew rate (note 6) pu src standard (3.3v ? 10%) 0.8 4 v/s overdrive (3.3v ? 10%) 2.7 20 5v pullup slew rate (note 6) pu src standard (5.0v ? 10%) 1.3 6 v/s overdrive (5.0v ? 10%) 3.4 31 power-on reset trip point v por 2.2 v 1-wire timing (note 15) see figures 4, 5, and 6 write 1/read low time t w1l standard 7.6 8 8.4 s overdrive 0.9 1 1.1 read sample time t msr standard 13.3 14 15 s overdrive 1.4 1.5 1.8 1-wire time slot t slot standard 65.8 69.3 72.8 s overdrive 9.9 10.5 11.0 fall time high-to-low at standard speed (note 6) t f1 3.3v to 0v (note 5) 0.54 3.0 s 5.0v to 0v (note 5) 0.55 2.2 fall time high-to-low at overdrive speed (note 6) 3.3v to 0v (note 5) 0.10 0.59 5.0v to 0v (note 5) 0.09 0.44 DS2482-800: 8-channel 1-wire master 3 of 23 parameter symbol conditions min typ max units write 0 low time t w0l standard 60 64 68 s overdrive 7.1 7.5 7.9 write 0 recovery time t rec0 standard 5.0 5.3 5.6 s overdrive 2.8 3.0 3.2 reset low time t rstl standard 570 600 630 s overdrive 68.4 72 75.6 presence-detect sample time t msp standard 66.5 70 73.5 s overdrive 7.1 7.5 7.9 sampling for short and interrupt t si standard 7.6 8 8.4 s overdrive 0.7 0.75 0.8 reset high time t rsth standard 554.8 584 613.2 s overdrive 70.3 74 77.7 i 2 c-pins (note 7) see figure 9 low level input voltage v il v cc = 2.9v to 3.7v -0.5 0.25 v cc v v cc = 4.5v to 5.5v 0.22 v cc high level input voltage v ih 0.7 v cc v cc + 0.5v v hysteresis of schmitt trigger inputs v hys 0.05 v cc v low level output voltage at 3ma sink current v ol 0.4 v output fall time from v ihmin to v ilmax with a bus capacitance from 10pf to 400pf t of 60 250 ns pulse width of spikes that are suppressed by the input filter t sp sda and scl pins only 50 ns input current each i/o pin with an input voltage between 0.1v ccma x and 0.9v ccmax i i (notes 8, 9) -10 +10 a input capacitance c i (note 8) 10 pf scl clock frequency f scl 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd:sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (notes 10, 11) 0.9 s data setup time t su:dat (note 12) 250 ns setup time for stop condition t su:sto 0.6 s bus free time between a stop and start condition t buf 1.3 s capacitive load for each bus line c b (note 13) 400 pf oscillator warm-up time t oscwup (note 14) 100 s DS2482-800: 8-channel 1-wire master 4 of 23 note 5: fall time high to low (t f1 ) is derived from pd src , referenced from 0.9 v cc to 0.1 v cc . note 6: these values apply at full load, i.e., 1nf at standard speed and 0.3nf at overdrive speed. for reduced load, the pulldown slew rate is slightly faster. note 7: all i 2 c timing values are referred to v ihmin and v ilma x levels. note 8: applies to sda, scl, and ad0, ad1, ad2. note 9: i/o pins of the ds2482 do not obstruct the sda and scl lines if v cc is switched off. note 10: the ds2482 provides a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: the maximum t hd : dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 12: a fast-mode i 2 c -bus device can be used in a standard-mode i 2 c -bus system, but the requirement t su : dat ? 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line tr max + t su : dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c -bus specification) before the scl line is released. note 13: c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times according to i 2 c-bus specification v2.1 are allowed. note 14: i 2 c communication should not take place for the max t oscwup time following a power-on reset. note 15: except for t f1 , all 1-wire timing specifications and t apuot are derived from the same timing circuit. therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in the same direction and by the same degree. pin description note 1: operating current with 1-wire write byte sequence followed by continuous read of status register at 400khz in overdrive. note 2: with standard speed the total capacitive load of the 1-wire bus should not exceed 1nf, otherwise the passive pullup on threshold v il1 may not be reached in the available time. with overdrive speed the capacitive load on the 1-wire bus must not exceed 300pf. note 3: active pullup guaranteed to turn on between v il1max and v ih1min . note 4: active or resistive pullup choice is configurable. pin name function 1 io3 io driver for 1-wire line #3 2 scl i 2 c serial clock input; must be tied to v cc through a pullup resistor. 3 sda i 2 c serial data input/output; must be tied to v cc through a pullup resistor. 4 v cc power supply input 5 nc not connected 6 ad2 i 2 c address inputs; must be tied to v cc or gnd. these inputs determine the i 2 c slave address of the device, see figure 8. 7 ad1 8 ad0 9 io7 io driver for 1-wire line #7 10 io6 io driver for 1-wire line #6 11 io5 io driver for 1-wire line #5 12 io4 io driver for 1-wire line #4 13 gnd ground reference 14 io0 io driver for 1-wire line #0 15 io1 io driver for 1-wire line #1 16 io2 io driver for 1-wire line #2 DS2482-800: 8-channel 1-wire master 5 of 23 figure 1. block diagram i2c interface controller sda scl config register i/o controller status register line xcvr channel select line xcvr line xcvr line xcvr line xcvr line xcvr line xcvr line xcvr a d0 a d1 a d2 io0 io1 io2 io3 io4 io5 io6 io7 read data register t-time osc detailed description the DS2482-800 is a self-timed 8-channel 1-wire master, which supports ad vanced 1-wire waveform features including standard and overdrive speeds, active pullup, and strong pullup for power de livery. once supplied with command and data, the i/o controller of the ds2482 perform s time-critical 1-wire commu nication functions such as reset/presence detect cycle, read-byte, write-byte, si ngle-bit r/w and triplet for rom search, without requiring interaction with the host processor. the host obtains feedba ck (completion of a 1-wire function, presence pulse, 1-wire short, search direction taken) through the status register and dat a through the read data register. the ds2482 communicates with a host processor through its i 2 c bus interface in standard-mode or in fast-mode. the logic state of three address pins (2 address pi ns with the 1-channel version) determines the i 2 c slave address of the ds2482, allowing up to 8 devices operating on the same bus segment without requiring a hub. device registers the ds2482 has four registers that the i 2 c host can read: channel selection, configuration, status, and read data. these registers are addressed by a read pointer. the position of the read pointer, i.e., the register that the host will read in a subsequent read access, is defined by the instruction that the has ds2482 executed last. the host has read and write access to the channel selection and configuration registers to select one of several 1-wire channels and to enable certain 1-wire features. DS2482-800: 8-channel 1-wire master 6 of 23 channel selection register the content of the channel selection r egister specifies which of the channels is selected and will be the target of subsequent 1-wire communication commands. the ds 2482-800 supports eight 1-wire communication channels io0 to io7. only one of these channels can be active/s elected at any time. once selected, a 1-wire channel remains selected until a different channel is selected through the channel select command or by initiating a device reset. after a device reset (power-up cycle or init iated by the device reset command) the io0 channel is selected. configuration register the ds2482 supports allows three 1-wire features that are enabled or selected through the configurat ion register. these features are: ? active pullup (apu) ? strong pullup (spu) ? 1-wire speed (1ws) these features can be selected in an y combination. they apply equally to all 1-wire channels. while apu, ppm and 1ws maintain their state, spu returns to its inac tive state as soon as the strong pullup has ended. configuration register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ws spu 1 apu 1ws spu 0 apu after a device reset (power-up cycle or initiated by the device reset comm and) the configuration register reads 00h. when writing to the confi guration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. active pullup (apu) the apu bit controls whether an active pullup (cont rolled slew-rate transistor) or a passive pullup (r wpu resistor) will be used to drive a 1-wire line from low to high. when apu = 0, active pullup is disabled (resistor mode). active pullup should always be selected unless there is only a single slave on the 1-wire line. the active pullup does not apply to the rising edge of a presence pulse or a recovery after a short on the 1-wire line. the circuit that controls rising edges (figure 2) operates as follows: at t1 the pulldown (from ds2482 or 1-wire slave) ends. from this point on t he 1-wire bus is pulled high through r wpu internal to the ds2482. v cc and the capacitive load of the 1-wire line determine the slope. in ca se that active pullup is disabled (apu = 0), the resistive pullup continues, as represented by the solid line. with active pullup enabled (apu = 1), when at t2 the voltage has reached a level between v il1max and v ih1min , the ds2482 actively pulls the 1-wire line high applying a controlled slew rate, as represented by the dashed line. the active pullup continues until t apuot is expired at t3. from that time on the resistive pull up will continue. figure 2. rising edge pullup v cc 0v 1-wire bus is dischar g ed v il1max v ih1min t apuot t 1 t 2 t 3 a pu = 1 a pu = 0 DS2482-800: 8-channel 1-wire master 7 of 23 strong pullup (spu) the spu bit controls whether the ds2482 applies a low-impedance pullup to v cc on the 1-wire line after the last bit of either a 1-wire write byte command or after a 1-wire single bit command has completed. the strong pullup feature is commonly used with 1-wire eeprom devic es when copying scratchpad da ta to the main memory or when performing a sha-1 computation, and with paras itically powered temperature sensors or a-to-d converters. the respective device data sheets specify the location in the communications protocol after which the strong pullup should be applied. the spu bit in the conf iguration register of the ds 2482 must be set immediately prior to issuing the command that puts the 1-wire devi ce into the state where it needs the extra power. if spu is 1, the ds2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts, regardless of the apu bit setting. however, in contrast to setting apu = 1 for active pullup, the low-impedance pullup will not end after t apuot is expired. instead, as shown in figure 3, the low-impedance pullup remains active until: a) the next 1-wire communication command (the typical case), b) by writing to the configuration register with the spu bit being 0 (alternative), or c) by issuing the device reset command. additionally, when the pullup ends, the spu bit is automatically reset to 0. using the str ong pullup does not change the state of the apu bit in the configuration register. note: strong pullup also affects the 1-wire reset command. if enabled, it can cause incorrect reading of the presence pulse and may cause a violation of the device's absolute maximum rating. figure 3. low-impedance pullup timing v cc 0v write 1 write 0 edges with active pull-up pull-up ds2482 pull-down ds2482 low impedance pull-up next time slot t slot last bit of 1-wire write byte or 1-wire single bit function DS2482-800: 8-channel 1-wire master 8 of 23 1-wire speed (1ws) the 1ws bit determines the timing of any 1-wire communication generated by the ds2482. all 1-wire slave devices support standard speed (1ws = 0), where the transfer of a single bit (t slot in figure 3) is completed within 65s. many 1-wire device can also co mmunicate at a higher data rate, called overdrive speed. to change from standard to overdrive speed, a 1-wire device needs to re ceive an overdrive skip rom or overdrive match rom command, as explained in the device data sheets. the chan ge in speed occurs immediately after the 1-wire device has received the speed-changing command code. the ds2482 must take part in this speed change to stay synchronized. this is accomplished by writing to the configuration register with the 1ws bit being 1 immediately after the 1-wire byte command that changes the speed of a 1 -wire device. writing to t he configuration register with the 1ws bit being 0 followed by a 1-wire reset command changes the ds2482 and any 1-wire devices on the active 1-wire line back to standard speed. status register the read-only status register is the general means for th e ds2482 to report bit-type data from the 1-wire side, 1-wire busy status and its own rese t status to the host processor. all 1-wire communication commands and the device reset command position the read pointer at the stat us register for the host processor to read with minimal protocol overhead. status information is updated during the execution of cert ain commands only. details are given in the description of the various status bits below. status register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir tsb sbr rst ll sd ppd 1wb 1-wire busy (1wb) the 1wb bit reports to the host processor whether the 1-wire line is busy. during 1-wire communication 1wb is 1; once the command is completed, 1wb returns to its def ault 0. details on when 1wb changes state and for how long it remains at 1 are found in the function commands section. presence pulse detect (ppd) the ppd bit is updated with every 1-wire reset command. if the ds2482 detects a pres ence pulse from a 1-wire device at t msp during the presence detect cycle, the ppd bit will be set to 1. this bit will return to its default 0 if there is no presence pulse or if the 1-wire line is shorted during a subsequent 1-wire reset command. short detected (sd) the sd bit is updated with every 1-wire reset command. if the ds2482 detects a logic 0 on the 1-wire line at t si during the presence detect cycle, the sd bit will be set to 1. this bit will return to its default 0 with a subsequent 1-wire reset command provided that the short has been re moved. if sd is 1, ppd will be 0. the ds2482 cannot distinguish between a short and a ds1994 or ds2404 signa ling a 1-wire interrupt. for this reason, if a ds2404/ds1994 is used in the applicati on, the interrupt function must be di sabled. the interrupt signaling is explained in the respective device data sheets. logic level (ll) the ll bit reports the logic state of the active 1-wire li ne without initiating any 1-wire communication. the 1-wire line is sampled for this purpose every time the status register is read. the sampling and updating of the ll bit takes place when the host processor has addressed the ds2482 in read mode (during the acknowledge cycle), provided that the read pointer is positioned at the status register. device reset (rst) if the rst bit is 1, the ds2482 has performed an internal reset cycle, either caused by a power-on reset or from executing the device reset command. the rst bit is cl eared automatically when the ds2482 executes a write configuration command to restore the sele ction of the desired 1-wire features. DS2482-800: 8-channel 1-wire master 9 of 23 single bit result (sbr) the sbr bit reports the logic state of the active 1-wire line sampled at t msr of a 1-wire single bit command or the first bit of a 1-wire triplet command. the power-on default of sbr is 0. if the 1-wire single bit command sends a 0-bit, sbr should be 0. with a 1-wire triplet command, sbr could be 0 as well as 1, depending on the response of the 1-wire devices connected. the same result applie s to a 1-wire single bit command that sends a 1-bit. triplet second bit (tsb) the tsb bit reports the logic state of the active 1-wire line sampled at t msr of the second bit of a 1-wire triplet command. the power-on default of tsb is 0. this bit is updated only with a 1-wire triplet command and has no function with other commands. branch direction taken (dir) whenever a 1-write triplet command is executed, this bit reports to the host processor the search direction that was chosen by the 3rd bit of the triplet. the power-on def ault of dir is 0. this bit is updated only with a 1-wire triplet command and has no function with other commands. for additional information see the description of the 1-wire triplet command and application note 187: 1-wire search algorithm . function commands the ds2482 understands nine function commands, whic h fall into four categories: device control, i 2 c communication, 1-wire setup and 1-wire communication. the feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information. the host processor sends these commands and applicable pa rameters as strings of one or two bytes using the i 2 c interface. the i 2 c protocol requires that each byte be acknowled ged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. details of the i 2 c protocol including acknowledge are found in the i 2 c interface description of this document. device reset command code f0h command parameter none description performs a global reset of device state machine logic, which in turn selects io0 as the active 1-wire channel. terminates any ongoing 1-wire communication. typical use device initialization after power-up; re -initialization (reset) as desired. restriction none (can be executed at any time) error response none command duration maximum 525ns, counted from falling scl edge of the command code acknowledge bit. 1-wire activity ends maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling) status bits affected rst set to 1, 1wb, ppd, sd, sbr, tsb, dir set to 0 configuration bits affected 1ws, apu, spu set to 0 DS2482-800: 8-channel 1-wire master 10 of 23 set read pointer command code e1h command parameter pointer code description sets the read pointer to the specified register. overwrites the read pointer position of any 1-wire communication command in progress. typical use to prepare reading the result from a 1-wire byte command; random read access of registers. restriction none (can be executed at any time) error response if the pointer code is not valid, the pointer code will not be acknowledged and the command will be ignored. command duration none; the read pointer is updated on the rising scl edge of the pointer code acknowledge bit. 1-wire activity not affected read pointer position as specified by the pointer code status bits affected none configuration bits affected none valid pointer codes write configuration command code d2h command parameter configuration byte description writes a new configuration byte. the new settings take effect immediately. note: when writing to the configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. typical use defining the features for subs equent 1-wire communication. restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code and parameter will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration none; the configuration register is updated on the rising scl edge of the configuration byte acknowledge bit. 1-wire activity none read pointer position configuration register (to verify write) status bits affected rst set to 0 configuration bits affected 1ws, spu, apu updated register selection code status register f0h read data register e1h channel selection register d2h configuration register c3h DS2482-800: 8-channel 1-wire master 11 of 23 channel select command code c3h command parameter selection code description sets the 1-wire io channel for subsequent 1-wire communication commands. note: the selection code read back is different from the code written. see the table below for the respective values. typical use selecting a 1-wire io channel other that io0; randomly selecting one of the available 1-wire io channels. restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code and parameter will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. if the selection code is not valid, the selection code will not be acknowledged and the command will be ignored. command duration none; the channel selection register is updated on the rising scl edge of the selection code acknowledge bit. 1-wire activity none read pointer position channel selection regist er (to verify write) status bits affected none configuration bits affected none valid channel selection codes channel selection code (to be written) code (read back) channel io0 (default) f0h b8h channel io1 e1h b1h channel io2 d2h aah channel io3 c3h a3h channel io4 b4h 9ch channel io5 a5h 95h channel io6 96h 8eh channel io7 87h 87h figure 4. 1-wire reset/presence detect cycle pullup ds2482 pulldown 1-w slave pulldown t rstl t rsth reset pulse presence/short detect presence pulse v cc v ih1 v il1 0 v t f1 t si t msp a pu controlled edge resistive pullup DS2482-800: 8-channel 1-wire master 12 of 23 1-wire reset command code b4h command parameter none description generates a 1-wire reset/presence detect cycle (figure 4) at the selected io channel. the state of the 1-wire line is sampled at t si and t msp and the result is reported to the host pr ocessor through the status register, bits ppd and sd. typical use to initiate or end any 1-wire communication sequence. restriction 1-wire activity must have ended before the ds2482 can process this command. strong pullup (see spu bit) should not be used in conjunction with the 1-wire reset command. if spu is enabled, the ppd bit may not be valid and may cause a violation of the device's absolute maximum rating. error response command code will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration t rstl + t rsth + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling) status bits affected 1wb (set to 1 for t rstl + t rsth ), ppd is updated at t rstl + t msp , sd is updated at t rstl + t si configuration bits affected 1ws, apu, spu apply 1-wire single bit command code 87h command parameter bit byte description generates a single 1-wire time slot with a bit value ?v? as specified by the bit byte at the selected 1-wire io channel. a ?v? value of 0b will generate a write-zero time slot (figure 5), a va lue of 1b will generate a write one slot, which also functions as a read data time slot (figure 6). in either case the logic level at the 1-wire line is tested at t msr and sbr is updated. typical use to perform single bit writes or reads on a 1-wire io channel when single bit communication is necessary (the exception). restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code and bit byte will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (ms bit) of the bit byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the ms bit of the bit byte. read pointer position status register (for busy polling and data reading) status bits affected 1wb (set to 1 for t slot ) sbr is updated at t msr dir (may change its state) configuration bits affected 1ws, apu, spu apply bit allocation in the bit byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x x = don?t care DS2482-800: 8-channel 1-wire master 13 of 23 figure 5. write- 0 time slot pullup (see fig. 2) ds2482 pulldown t rec0 v cc v ih1 v il1 0v t f1 t slot t w0l t msr figure 6. write-1 and read-data time slot pullup (see fig. 2) ds2482 pulldown 1-w slave pulldown v cc v ih1 v il1 0v t f1 t slot t w1l t msr note on figure 7 : depending on its internal state, a 1-wire slave device will transmit data to its master (e.g., the ds2482). when responding with a 0, a 1-wire slave will start pulling the line low during t w1l ; its internal timing generator determines when this pulldown ends and the volt age starts rising again. when responding with a 1, a 1-wire slave will not hold the line low at a ll, and the voltage starts rising as soon as t w1l is over. 1-wire device data sheets use the term t rl instead of t w1l to describe a read-data time slot. technically, t rl and t w1l have identical specifications and cannot be distinguished from each other. 1-wire write byte command code a5h command parameter data byte description writes single data byte to selected 1-wire io channel. typical use to write commands or data to a 1-wire io channel; equivalent to executing eight 1-wire single bit commands, but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code and data byte will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration 8 t slot + maximum 262.5ns, counted from falling edge of the last bit (ls bit) of the data byte. 1-wire activity begins maximum 262.5ns after falling scl edge of the ls bit of the data byte (i.e., before the data byte acknowledge). note : the bit order on the i 2 c bus and the 1-wire line is different. (1-wire: ls-bit first; i 2 c: ms-bit first) therefore, 1-wire activity cannot begin before the ds2482 has received the full data byte. read pointer position status register (for busy polling) status bits affected 1wb (set to 1 for 8 t slot ) configuration bits affected 1ws, spu, apu apply DS2482-800: 8-channel 1-wire master 14 of 23 1-wire read byte command code 96h command parameter none description generates eight read data time slots on the selected 1-wire io channel and stores result in the read data register. typical use to read data from a 1-wire io channel; equivalent to executing eight 1-wire single bit commands with v = 1 (write 1 time slot), but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration 8 t slot + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling) note : to read the data byte received from the 1-wire io channel, issue the set read pointer command and select the read data register. then access the ds2482 in read mode. status bits affected 1wb (set to 1 for 8 t slot ) configuration bits affected 1ws, apu apply 1-wire triplet command code 78h command parameter direction byte description generates three times slots, two read-t ime slots and one-write time slot, at the selected 1-wire io channel. the type of write-time slot depends on the result of the read-time slots and the direction byte. the direction byte determines the type of write-time slot if both read-time slots are 0 (a typical case). in this case the ds2482 will generate a write-1 time slot if v = 1 and a write-0 time slot if v = 0. if the read-time slots are 0 and 1, there will follow a write 0 time slot. if the read-time slots are 1 and 0, there will follow a write 1 time slot. if the read-time slots are both 1 (error case), the subsequent write time slot will be a write 1. typical use to perform a 1-wire search rom sequence; a full sequence requires this command to be executed 64 times to identify and address one device. restriction 1-wire activity must have ended before the ds2482 can process this command. error response command code and direction byte will not be acknowledged if 1wb = 1 at the time the command code is received and the command will be ignored. command duration 3 t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (ms bit) of the direction byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the ms bit of the direction byte. read pointer position status register (for busy polling) status bits affected 1wb (set to 1 for 3 t slot ) sbr is updated at the first t msr tsb and dir are updated at the second t msr (i.e., at t slot + t msr ) configuration bits affected 1ws, apu apply DS2482-800: 8-channel 1-wire master 15 of 23 bit allocation in the direction byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x x = don?t care i 2 c interface general characteristics the i 2 c bus uses a data line (sda) plus a clock signal (scl) for communication. both sda and scl are bidirectional lines, connected to a positive supply voltage through a pullup resistor. when there is no communication, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-and function. data on the i 2 c bus can be transferred at rates of up to 100kbps in the standard-mode, up to 400kbps in the fast-mode. the ds2482 works in both modes. a device that sends data on the bus is defined as a tran smitter, and a device receiving data as a receiver. the device that controls the communication is called a ?maste r.? the devices that are controlled by the master are ?slaves.? to be individually accessed, each device must have a slave address that doe s not conflict with other devices on the bus. data transfers may be initiated only when the bus is not busy. the master generates the serial clock (scl), controls the bus access, generates the start and stop conditions, and determines the number of data bytes transferred between start and stop (figure 7). data is tr ansferred in bytes with the most significant bit being transmitted first. after each byte follows an acknowledge bit to allow synchronization between master and slave. figure 7. i 2 c protocol overview scl sda 12 678 a ck 9 9 12 8 ms-bit r/ w slave address ack bit acknowledgment from receiver ack bit start condition a ck repeated if more bytes are transferred stop condition repeated start condition idle slave address the slave address to which the ds2482 responds is shown in figure 8. the logic states at the address pins ad0, ad1 and ad2 determine the value of the address bits a0, a1, and a2. the address pins allow the device to respond to one of eight possible slave addresses. the slave address is part of t he slave-address/control byte. the last bit of the slave-address/control byte (r/ w ) defines the data direction. when set to a 0, subsequent data will flow from master to slave (write ac cess); when set to a 1, data will flow fr om slave to master (read access). DS2482-800: 8-channel 1-wire master 16 of 23 figure 8. ds2482 slave address a6 a5 a4 a3 a2 a1 a0 0 0 1 1 ad2 ad1 ad0 r/w 7-bit slave address most signi- ficant bit determines read or write ad2, ad1, ad0 pin states i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. the timing references are defined in figure 9. bus idle or not busy: both, sda and scl, are inactive and in their logic high states. start condition: to initiate communication with a slave, the master has to generate a start condition. a start condition is defined as a change in state of sda from high to low while scl remains high. stop condition: to end communication with a slave, the master has to generate a stop condition. a stop condition is defined as a change in state of sda from low to high while scl remains high. repeated start condition: repeated starts are commonly used for read accesses to select a specific data source or address to read from. the master can use a repeated start condition at the end of a data transfer to immediately initiate a new data transfer following the current one. a repeated start condition is generated the same way as a normal start condition, but without leaving the bus idle after a stop condition. data valid: with the exception of the start and stop conditi on, transitions of sda may occur only during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl, see figure 9). there is one clock pulse per bit of data. data is shifted into the receiving device during the rising edge of the scl. when finished with writing, the master must release t he sda line for a sufficient amount of setup time (minimum t su:dat + t r in figure 9) before the next rising edge of scl to start reading. the slave shifts out each data bit on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. the master generates all scl clock pulses, including those needed to read from a slave. acknowledge: usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. the master must generate a clock pul se that is associated with this acknowledge bit. a device that acknowledges must pull sda low during the acknowle dge clock pulse in such a way that sda is stable low during the high period of the ackn owledge-related clock pulse plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl). not acknowledged by slave: a slave device may be unable to receive or transmit data, e.g., because it is busy performing some real-time function. in this case the sl ave device will not acknowledge its slave address and leave the sda line high. a slave device that is ready to communi cate will acknowledge at least its slav e address. however, some time later the slave may refuse to accept data, e.g., because of an invalid command code or parameter. in this case the slave device will not acknowledge any of the by tes that it refuses and will leave sda high. in either case, after a slave has failed to acknowledge, the master first needs to gene rate a repeated start condition or a stop condition followed by a start condition to begin a new data transfer. DS2482-800: 8-channel 1-wire master 17 of 23 not acknowledged by master: at some time when receiving data, the master must signal an end of data to the slave device. to achieve this, the master does not acknowledge the last byte that it has received from the slave. in response, the slave releases sda, allowing t he master to generate the stop condition. figure 9. i 2 c timing diagram scl sda stop start t buf t hd:sta t low t r t hd:dat t high t su:dat repeated start t su:sta t f t hd:sta t sp t su:sto spike suppression note: timing is referenced to v ilmax and v ihmin . writing to the ds2482 to write to the ds2482, the master must access the device in write mode, i.e ., the slave address must be sent with the direction bit set to 0. the next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. the ds2482 will acknowledge valid command codes and expected/valid command parameters. additional bytes or invalid command parameters will never be acknowledged. reading from the ds2482 to read from the ds2482, the master must access the device in read mode, i. e., the slave address must be sent with the direction bit set to 1. the read pointer determines the register that the master will read from. the master may continue reading the same register over and over agai n, without having to re-addre ss the device, e. g., to watch the 1wb changing from 1 to 0. to read from a differ ent register, the master must issue the set read pointer command and then access the ds2482 again in read mode. i 2 c communication?legend symbol description symbol description s start condition drst command "device reset", f0h ad,0 select ds2482 for write access wcfg command "write configuration", d2h ad,1 select ds2482 for read access chsl command "channel select", c3h sr repeated start condition srp command "set read pointer", e1h p stop condition 1wrs command "1-wire reset", b4h a acknowledged 1wwb command "1-wire write byte", a5h a\ not acknowledged 1wrb command "1-wire read byte", 96h (idle) bus not busy 1wsb command "1-wire single bit", 87h DS2482-800: 8-channel 1-wire master 18 of 23 data direction codes master-to-slave slave-to-master i 2 c communication examples device reset, e.g., after power-up s ad,0 a drst a sr ad,1 a DS2482-800: 8-channel 1-wire master 19 of 23 1-wire reset, e.g., to begin or end 1-wire communication case a: 1-wire idle (1wb = 0), no busy polling to read the result s ad,0 a 1wrs a p (idle) s ad,1 a DS2482-800: 8-channel 1-wire master 20 of 23 case c: 1-wire idle (1wb = 0), busy pol ling until the 1-wire command is completed. s ad,0 a 1wrb a sr ad,1 a DS2482-800: 8-channel 1-wire master 21 of 23 case c: 1-wire busy (1wb = 1) s ad,0 a 1wt a\ p the master should stop and restart as soon as the ds2482 does not acknowledge the command code. figure 10. application schematic application information sda and scl pullup resistors sda is an open-drain output on the ds2482 that requires a pullup resistor to realize high logic levels. because the ds2482 uses scl only as input (no clock stretching) the master can drive scl either through an open- drain/collector output with a pullup resistor or a push-pull output. pullup resistor r p sizing according to the i 2 c specification, a slave device must be able to sink at least 3ma at a v ol of 0.4v. this dc condition determines the minimum value of the pullup resistor: rpmin = (v cc - 0.4v)/3ma. with an operating voltage of 5.5v, the minimum value for the pullup resistor is 1.7k ? . the "minimum rp" line in figure 11 shows how the minimum pullup resistor cha nges with the operating voltage. for i 2 c systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. the maximum bus capacitance c b is 400pf. the maximum rise time at standard speed must not exceed 1000ns and 300ns at fast speed. assuming maximum rise time, the maxi mum resistor value at any given capacitance c b is calculated as: rpmaxs = 1000ns/(c b *ln(7/3)) (standard speed) and rpmaxf = 300ns/(c b *ln(7/3)) (fast speed). for a bus capacitance of 400pf the maximum pullup resistor values are 2.95k ? at standard speed and 885 ? at fast speed. a value between of 1.7k ? and 2.95k ? meets all requirements at standard speed. since a 885 ? pullup resistor, as would be required to meet the rise time specification at fast speed and 400pf bus capacitance, is lower than rpmin at 5.5v , a different approach is necessary. the "max. load?" line in figure 11 is generated by first calculating the minimum pullup resistor at any given operating voltage ("minimum rp" line) and then calculating the respective bus capacita nce that yields a rise time of 300ns. ds2482 - 800: 8- channel 1 - wire master 22 of 23 only for pullup voltages of 3v and lower can the maximum permissible bus capacitance of 400pf be maintained. a reduced bus capacitance of 300pf is acceptable for pullup voltages of 4v and lower. for fast speed operation at any pullup voltage, the bus capacitance must not exceed 200pf. the corresponding pullup resistor value at the voltage is indicated by the "minimum rp" line. figure 11. i 2 c fast mode pullup resistor selection chart 0 400 800 1200 1600 2000 1 2 3 4 5 pull-up voltage minimum rp (ohms) 0 100 200 300 400 500 load (pf) "minimum rp" max. load at min. rp fast mode package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/pa ckages . note that a "+", "#", or " - " in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so (150 mil s) s16+5 21-0041 90-0097 DS2482-800: 8-channel 1-wire master 23 of 23 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 6/04 initial release ? 11/04 ec table changes (pu src and t f1 ) 2 upper i 2 c slave address bits changed from 0110b to 0011b 16 8/08 removed the 1-wire line termination resistor and references to it from the typical operating circuit and figure 11. deleted i 2 c trademark note; added package information section. 1, 21, 22 11/09 conversion to lead (pb) free product. 1 removed the presence pulse masking feature. 1, 3, 4, 5, 6, 7, 9, 10, 11, 12 revised the recommendation on the use of active pullup. 6 12/11 updated the soldering information. 2 added a note to strong pullup (spu) description. 7 updated the 1-wire reset command description, sections restriction and configuration bits affected . 12 added the land pattern column to package information section. 22 |
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